This invention relates to burst read accesses, and more particularly to predicting burst-lengths of bus transactions.
Traditional main memories often employ caches to speed up access times. A subset of the data in the main memory is stored in a cache memory. When the requested data is in the cache, access is more rapid. Each entry in the cache typically contains a portion of its address, such as a tag.
Various prediction mechanisms exist for pre-fetching data into the cache. For example, when the data is program code, the next several data items can be pre-fetched into the cache, since memory accesses may occur in a linear sequence of addresses. For more random data accesses, pre-fetching may be less effective.
Such prediction methods used for cache memories are less useful for input-output (IO) bus transactions. IO buses often connect to a variety of peripheral devices. Some devices may transfer a small amount of data while other devices transfer large blocks of data at once. Traditional cache-memory prediction methods fail under these non-homogenous conditions.
One popular IO bus is the Peripheral Component Interconnect (PCI), used in many personal computers (PCs), computer servers, storage and network systems. The PCI bus can connect to a wide variety of devices, including memory, disk drives, graphics systems, and controllers to other buses, such as Universal-Serial-Bus (USB) and FireWire (IEEE 1394). A wide variety of input-output devices can be accessed through these other buses, such as memory cards, pointing devices (mice), music devices, printers, etc. The types of bus accesses for this wide variety of devices is quite varied. Predicting ahead in such a varied environment is challenging, yet a good prediction scheme could improve bus performance.
What is desired is a prediction method for an input-output bus that connects to a wide variety of devices. A bus-transaction prediction system is desired for accesses over a PCI bus.